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Philips Semiconductors
Product specification
Electronic ballast controller circuit
NE5565
DESCRIPTION
The Electronic Ballast controller chip has been designed in a bipolar process. It is housed in a 20-lead dual-in-line plastic package. The control chip contains the equivalent of two (2) switched mode power supply control circuits. The first SMPS controller is a DC-to-DC converter operating in the discontinuous current conduction mode. It is used as a PFC in the ballast system to provide a DC voltage step-up function, good AC power factor, low AC current harmonic distortion, and circuit protection against some types of AC voltage transients. The PFC uses pulse width modulation to control the power transfer with an external MOS power transistor. The second SMPS circuit is a half-bridge oscillator circuit. It converts the DC output voltage of the PFC into a high frequency AC voltage for operating lamps. Power transfer in this circuit is controlled by changing the switch frequency. The half-bridge controller circuit is capable of driving two external high voltage MOS power transistors and it has circuits to regulate the lamp current, limit the peak lamp voltage, and protect the power switches during fault conditions. This electronic ballast controller circuit has the capability of being used in a dimming application.
PIN CONFIGURATION
N Package
CT CP 1 2 20 DCOUT 19 DC 18 OV 17 PF 16 VREF 15 IPRIM 14 OUTH 13 VCC 12 OUTP 11 GND
DMAX 3 RT RXCX 4 5
VLAMP 6 CRECT 7 LI2 8 LI 9 CSI 10
SL00524
Figure 1. Pin Configuration
FEATURES:
* Complete PFC correction and dimming ballast control on one IC * Low line current distortion PFC
ORDERING INFORMATION
DESCRIPTION 20-Pin Plastic Dual-In-Line Package (DIP)
* Selectable variable frequency modes * Programmable pre-hit and ignition * Lamp over-voltage protection * PFC over-voltage protection for preventing over-shooting due to
load removal
TEMPERATURE RANGE 0 to +85C
ORDER CODE NE5565N
DWG # SOT146-1
BLOCK DIAGRAM
VLAMP RXCX 6 5 4 VCC CRECT LI2 LI 7 8 9 3 DMAX CP CT RT
CSI
10
2 1
GND
11 12 20 DCOUT
OUTP
VCC
13
14 OUTH
15 IPRIM
16 VREF
17 18 PF OV
19 DC
SL00525
Figure 2. Block Diagram 1996 May 21 1 853-1835 16843
Philips Semiconductors
Product specification
Electronic ballast controller circuit
NE5565
AC LINE FLUORESCENT LAMPS POWER FACTOR CORRECTION CIRCUIT HALF-BRIDGE SQUARE WAVE OSCILLATOR
AC FILTER
DC SUPPLY
13 VCC PF
17
12 OUTP
10 CSI
11 GND
19 DC
18 OV OUTH
14
6
15 IPRIM
VLAMP
RXCX 5
VREF 16
RT 4
DMAX 3
CP 2
CT 1
DCOUT 20
CRECT 7
LI 9
LI2 8 R5
RT RX R1 R2 CX C1 CP CT C2 C3 R3
R4
DIMMING INPUT
SL00526
Figure 3. Typical Application: 2-Lamps Dimming Ballast
Voltage Regulator
The VREF output provides a regulated output voltage of 7.42V at the VREF pin. This voltage is used as a reference as well as the power supply of the control logic. It is based on a trimmed band gap voltage reference circuit. The nominal VCC voltage for the control chip is 12.7V. The VREF circuit requires a minimum of 9.3V before it can produce regulated output. The VREF output voltage has an absolute accuracy of 3.5% over the temperature range of 0C to 85C.
above the upper trip point, both PFC and half-bridge oscillator circuits become operational. When the VCC falls below the lower trip point of 10V, both PFC and half-bridge circuits are disabled. Once the half-bridge oscillator turns off, it is not allowed to turn back on until VCC exceeds the upper trip point and a minimum time delay, set by external components at the DMAX pin, has passed.
Start up Ckt
The Low Half-bridge Voltage Lock-out Circuit senses the DC output voltage of the PFC SMPS clrcuit. It is used to inhibit the lamp ignition sequence or frequency sweep of the half-bridge oscillator until the PFC output voltage has reached a pre-determined value. This value is set by external components. The PFC voltage is sensed by the over voltage input pin, OV. When this input exceeds 5/7 of VREF the frequency sweep is allowed to occur, thus beginning the lamp ignition sequence. The Over Voltage Protection Circuit prevents the PFC DC output voltage from exceeding a pre-determined value. When the voltage at the OV pin is greater than VREF the PFC buffer gate drive output OUTP is turned off. This prevents any further increase in PFC DC output voltage. The over voltage circuit only protects against an over voltage or over shoot generated by the PFC itself. This may occur during turn on when the SMPS is not loaded and the circuit is under damped. Transient voltages from the AC line are not suppressed by this circuit.
Lamp Voltage Regulator
Limits the maximum open circuit voltage across the lamp load during the pre-heat, ignition and lamp removal conditions. During steady state operation, the lamp voltage is governed by the arc voltage of the lamps, not by the control circuit. The lamp voltage comparator is used to sense when the voltage at the VLAMP pin exceeds VREF. At the time this occurs, the lamp voltage has reached its maximum allowed open circuit value and the circuit responds by producing a rapid frequency increase which reduces the voltage at the Vlamp pin. The RxCx time constant sets the frequency sweep time of the start up circuit. The frequency sweep range has a rate of 2:1.
Low Supply Lock-out Protection
Senses the DC power supply voltage at the VCC pin to determine when the PFC and half-bridge control circuits should turn on or off. This protection circuit uses a Schmitt trigger with a voltage reference to determine the upper and lower trip points of the power supply voltage. As the power supply voltage rises from 0V to a value just below the upper trip point of 11V, both the PFC and the half-bridge control circuits are held in the off state. Once the VCC voltage rises 1996 May 21 2
Capacitive Load Protection
Prevents failure of the half-bridge power transistors during lamp removal. It does this by limiting the operation of the half-bridge oscillator to frequencies above the resonant frequency of an
Philips Semiconductors
Product specification
Electronic ballast controller circuit
NE5565
external LC network driven by the bridge. At frequencies above resonance the primary voltage of the half-bridge LC load network leads the primary current in phase. The protection logic senses the LC network current phase relative to the half-bridge gate drive voltage to determine if a resonant condition exists. The Iprim input voltage represents the primary current signal from the external LC network. If the voltage at Iprim is more positive than -100mV when the gate drive signal is high, then a fault condition exists and the half-bridge oscillator frequency is swept high.
triggers the over current protection circuit this turns off the OUTP output and forces the external capacitor connected to DMAX to discharge when an over current condition occurs in the PFC input circuit. An over current condition is usually produced during the turn on transient of the SMPS or when the AC line voltage has a power interruption.
Power Factor Amplifier
Senses the phase and amplitude of a peak rectified AC line voltage in order to modulate the duty cycle of the PFC power switch. This is done to improve the sinusoidal wave shape of the AC line current. The power factor input is provided by the PF input pin. The voltage at this pin is 1V when the AC line voltage reaches its peak and 0V when the AC voltage is at its 0V crossing.
Half-Bridge Oscillator
Is a triangle wave generator used to produce a square wave signal for driving the half-bridge buffer circuit. The triangle wave appears on the Ct capacitor output pin. The oscillator frequency is governed by the value of the resistor connected to the Rt input and the value of the Ct capacitor.
DC Error Amplifier
Provides negative feedback control of the PFC DC output voltage. The DC pin senses the DC output voltage of the PFC through an external resistor voltage divider and filter network. The reference voltage for the DC error amplifier is VREF. The output of the amplifier is available at the DC out pin and an external capacitor is connected to this pin in order to remove switching frequency noise before its signal is applied to the pulse width modulator in the PWM oscillator circuit.
Output Buffer Drive
Convert the low level logic signals from the half-bridge oscillator and pulse width modulator into a 10V drive signal for the power switches. The OUTH half-bridge buffer/drive circuit will drive an external level shift scheme which will then be used to operate the half-bridge power switches. The OUTP output may directly drive a power MOSFET switch or an external level shift/power MOSFET combination.
Lamp Current Rectifier
Is used to provide negative feedback control of the average lamp current. An external lamp current transformer and load resistor are used to convert the lamp current signal into a voltage. This voltage is applied to the lamp current input pins, Li1 and Li2. The full wave rectified output is provided at CRECT pin. External resistors and a capacitor determine the gain and time constant of the circuit. A differential error amplifier compares the voltage of CRECT to an internal reference of 2/7 VREF and adjusts the half-bridge oscillator frequency so that the error voltage is minimized. This forces the average lamp current to be a constant.
Pulse Width Modulator
Generates a ramp voltage used to control the duty cycle of the PFC SMPS. The frequency of the pulse width modulator is set by the half-bridge oscillator. The ramp voltage appears at the CP output. It is synchronized to the half-bridge oscillator so that the beginning of the ramp occurs at the valley of the Ct triangle waveform. When the ramp voltage at CP exceeds the voltage at the DC out pin in the DC amplifier, the capacitor connected to CP is discharged. The period of the PFC gate drive pulse correspond to the CP ramp time. The maximum duty cycle, soft start function, and half-bridge off time are all controlled by the external capacitor and resistors connected to the DMAX pin.
Dimming
Dimming input should be an extra current put into charging C3 in addition to the current from Pin 7. This creates the same condition as higher voltage differential across Pins 8 and 9, hence, the IC reacts as if there is too much power applied to the lamps.
Over Current Protection
An over current is sensed by an external resistor connected to the current sense input pin, CSl. A voltage of minus 500mV at CSl
1996 May 21
3
Philips Semiconductors
Product specification
Electronic ballast controller circuit
NE5565
PIN DESCRIPTIONS/ABSOLUTE MAXIMUM RATINGS
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Name Ct CP DMAX Rt RxCx VLAMP CRECT Li2 Li1 CSl GND OUTP VCC OUTH IPRIM VREF PF OV DC DCOUT Function Half-Bridge oscillator capacitor PWM Capacitor for power factor correction circuit Max Duty Cycle, soft start, and time delay R/C input Resistor for setting the half-bridge frequency Start resistor and capacitor input for setting frequency sweep time Lamp voltage regulator input Lamp current rectifier capacitor input/dimming control input Lamp current differential inputs Current sense input for over-current protection Ground Gate drive output for the PFC Positive power supply voltage Gate drive output for the half-bridge DMOS Primary current sense input Regulated output voltage and reference Power factor input 0ver-voltage comparator input DC error amplifier input DC error amplifier output for connecting to external filter capacitor Rating 7 7 7 0.7V or 500A 7 14 7 1V to Li1, 7V or VREF -0.7V to GND +0.5 V / -2V 0 14 14 14 +1V / -1.5 V or 500A VCC 7 14 12 7 Units V V V V/A V V V V V V V V V V/A V V V V V
DC ELECTRICAL CHARACTERISTICS
VCC = +12.7V, TA = 25C; unless otherwise stated. SYMBOL DC Error Amplifier DC input clamp current DC bias current DC error amp reference DC output HIGH voltage Power Factor Amplifier PF input current PF transconductance Start-up Circuit RxCx input current RxCx threshold OV input current OV threshold HB lockout threshold Oscillator Rt voltage Ct HIGH current Ct LOW current Ct HIGH threshold Ct LOW threshold PWM CP HIGH threshold CP-to-DMAX threshold CP-to-DC output threshold 1996 May 21 4 DMAX = 4V DC = 4V 3.66 2.97 2.97 4.07 3.3 3.3 4.48 3.63 3.63 V V V RxCx=0V Rt=100A RxCx=6.5V Rt=100A -160 -80 4.14 2.23 .7 -200 -100 4.6 2.48 -240 -120 5.06 2.73 V A A V V OV = 5V 7.05 4.93 7.42 5.3 RxCx = 0.5V 1.51 1.59 -8 1.67 -8 7.79 5.67 A V A V V PF = 1V 65 100 -14 135 A A/V DC = 7V DC = 0V DC = VREF 7.05 5.4 7.42 -403 -690 -941 -1 7.79 6.6 A A V V PARAMETER TEST CONDITIONS LIMITS MIN TYP MAX UNITS
Philips Semiconductors
Product specification
Electronic ballast controller circuit
NE5565
DC ELECTRICAL CHARACTERISTICS (continued)
SYMBOL PWM (cont.) DMAX input current DMAX threshold Power Supply ISUPPLY static VCC VREF Supply voltage Reference voltage VREF tolerance VREF load current IREF short circuit current Buffer OUTP / OUTH LOW OUTP / OUTH HIGH OUTP / OUTH peak triangle wave current OUTP / OUTH pulse current Low supply upper trip point Low supply lower trip point Lamp Voltage Regulator VLAMP input current VLAMP threshold Load Protection IPRIM input current IPRlM negative threshold Over-current Protection CSI input current CSI threshold Rectifier (RLi = RLi2 = 4k, R3 = 20k; VRLi = Voltage input to RLi1; VRLi2 = 0V, Input to RLi2) Li input current CRECT output offset CRECT HIGH output CRECT gain CRECT error amp reference VRLi1 = VRLi2 = 0V VRLi1 = VRLi2 = 0V VRLi1 = 0.5V VRECT/VRLi1 4.42 8.86 2.01 4.66 9.33 2.12 -120 -200 -280 150 4.9 9.80 2.23 V A mV V CSI = -1V -60 -400 -100 -500 -140 -650 A mV IPRIM = 0V -60 -60 -100 -100 -140 -140 A mV VLAMP = 6.5V 7.05 7.42 -8 7.79 A V IPC = 40mA IPC = 250mA PULSE IPC = -40mA IPC = -250mA PULSE Magnetizing Gate capacitance current 10.45 9.5 11.0 10.0 10.2 8.1 40 250 11.55 10.5 mA mA V V 1 3 V VREF = 0V -30 TRIMMED VALUE 0 to 85C VCC = 12.7V 9 9.3 7.42 3.5 -5 18 14 mA V V % mA mA DMAX = 0.5V 0.95 1.06 -1 1.17 A V PARAMETER TEST CONDITIONS LIMITS MIN TYP MAX UNITS
1996 May 21
5
Philips Semiconductors
Product specification
Electronic ballast controller circuit
NE5565
DIP20: plastic dual in-line package; 20 leads (300 mil)
SOT146-1
1996 May 21
6

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